Ausdia Introduces Timing constraints Generation and Validation Add-on to Timevision at DAC 2013
  03 Jun, 2013 -    
Ausdia Receives Patent for System and Method for Automatically Managing Clock Relationships in Integrated Circuit Designs
  20 May, 2013 -
   
Ausdia Appoints EDA and Semiconductor Industry Expert Sanjay Lall to Board of Directors
  08 Nov, 2012 -    
EETimes Silicon 60: Hot startups to watch
  04 Oct, 2012 -    
Timing Closure Experts Launch New Company
  04 Jun, 2012 -    
EEtimes interview with Sam Appleton
  03 Sep, 2012 -    
We’re hiring @Ausdia
  14 May, 2012 - ...
   
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  14 May, 2012 - Follow us on twitter    
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  14 May, 2012 - Join our Linkedin Group    
  
 
Ausdia tops Gary Smith's "What to see at DAC" List
   
 
Learn about Ausdia - CEO Interview
   
DAC 2014 - Be There
  • "Ausdia developed the Timing Verification and signoff environment from ground up for a highly complex, hierarchical chip project. This chip included numerous clocks, high speed interfaces, and 3rd party soft / hard IP cores from various vendors....
     
      Michael Raam - Sr. VP of Engineering
      Mobilygen Corp (now part of Maxim)
  • "Ausdia worked closely with my design team to drive several highly complex blocks through synthesis, constraints and physical implementation. They also contributed heavily to fullchip timing verification and external IP timing verification. They played a big part in the project's...
     
      Amal Bommireddy - VP Engineering
      AMCC
  • "Ausdia was brought in to help finish off some high-priority items, including chip assembly, interface timing verification and toplevel timing closure. I was impressed with their work, and thanks partly to  their efforts we taped out a 1.3B transistor chip that worked first-time ...
     
      John B - VP Engineering
      Innovative Silicon Valley Server Startup
  
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