A solution for constraints development and verification, allowing
system-on-chip (SoC) and integrated circuit (IC) developers to
make massive productivity gains across the design flow.
A clean, consistent and correct set of timing constraints (SDC) is a necessity to get the best PPA (power, performance and area) from timing-driven implementation tools. Timevision Check SDC provides over 200 checks on the SDC, aids in the design of new SDC constraints, and works on RTL and gate-level designs from early RTL to signoff gate netlist.NEXT MODULE >
RTL to Gate Signoff Constraint Development Using Timevision presented by Arm
Verifying Clock Groups