Timevision™ Modules

A solution for constraints development and verification, allowing
system-on-chip (SoC) and integrated circuit (IC) developers to
make massive productivity gains across the design flow.

SOC Budgeter Check SDC Formal SDC SoC Hierarchy Mode-Merge Extracted Timing Model (ETM) Diff SDC Multi-Mode Coverage Design-For-Test (DFT) Clock Domain Crossing (CDC) Glitch

SOC Budgeter

Timevision SOC Budgeter handles the SDC integration and management tasks of hierarchical SoC design. However, the generation of timing budgets (allocation of allowable time between the SoC partitions) becomes paramount also. Timevision SOC Budgeter uses SDFs, timing reports and physical data (LEF/DEF) to produce and manage accurate timing budgets for the blocks used in hierarchical implementation flows.

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