A powerful and trusted design constraint development and verification
platform that allows system-on-chip (SoC) developers
to make massive productivity gains across the design flow.
A static timing analysis engine is necessary so that analysis is done that correlates exactly to the results of a signoff STA tool.
Clock Domain Crossing (CDC) Engine
Most CDC tools have their own "constraints" format. Spyglass for example has SGDC and tried to "standardize" on it, but most users reject it and convert SDC to SGDC. This conversion itself has bugs. Ausdia has chosen to just take the SDC and extend it where necessary for CDC purposes.
False path constraints are meant as a way to simplify verification in that they detail that paths from one part of the circuit to a certain other part of the circuit are never used, so there is no need to 'fix' its timing. Multicycle path (MCP) constraints except they detail the number of clock cycles it's expected to take to get to the other part. Formal verification techniques such as property checking can be employed to verify that these "exceptions" are correct or not. Timevision's formal engine can reads the exceptions, "synthesizes" a property check from the exception, and then formally verifies it. If we can't prove it, we can write a System Verilog Assertion (SVA) that is the same as the internal property check, so the users can run it through their simulation environment, use in conjunction with Jasper.
Timevision can also "search" the design for MCPs; the tool simply treats everything as if it was an MCP and gauges whether they can be proven.
Structural Analysis Engine
With Timevision's structural analysis engine, what the technology checks for are "rules" and engineers can report against the rule or category of rules. Rules can be turned on and off to waive specific checks or objects within rules. Beyond this,Timevision includes a complete debugging system that reports all of the analysis and data leading up to the rule violation.