Timevision™ Modules

A solution for constraints development and verification, allowing
system-on-chip (SoC) and integrated circuit (IC) developers to
make massive productivity gains across the design flow.

SOC Budgeter Check SDC Formal SDC SoC Hierarchy Mode-Merge Extracted Timing Model (ETM) Diff SDC Multi-Mode Coverage Design-For-Test (DFT) Clock Domain Crossing (CDC) Glitch

DIFF SDC

Designs and their associated timing constraints (SDC)s change often during the implementation flow. These changes raise issues with the implementation team of what changed and how it will affect their results.

Timevision Diff SDC checks two designs, either RTL or gate-level netlist, for changes in timing or functionality, giving the designer exact coverage on the difference between the two versions provided.

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