Timevision™ Modules

A solution for constraints development and verification, allowing
system-on-chip (SoC) and integrated circuit (IC) developers to
make massive productivity gains across the design flow.

SOC Budgeter Check SDC Formal SDC SoC Hierarchy Mode-Merge Extracted Timing Model (ETM) Diff SDC Multi-Mode Coverage Design-For-Test (DFT) Clock Domain Crossing (CDC) Glitch

DESIGN-FOR-TEST (DFT)

Common DFT techniques like lockup latch insertion and test clock assignment are often very hard to verify and can cause late-stage impacts on functional modes of SoC designs. Timevision DFT helps analyze DFT logic and its intersection with functional timing, reducing late stage schedule impacts from DFT errors and related coverage escapes.

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