A solution for constraints development and verification, allowing
system-on-chip (SoC) and integrated circuit (IC) developers to
make massive productivity gains across the design flow.
Modern techniques for logic synthesis and backend optimization can create logical glitch paths on asynchronous crossings – places in restructured logic where a small pulse can propagate through the post-implementation design and be sampled at an endpoint. This is of particular importance to complex asynchronous reset networks.
Timevision Glitch uses static formal verification techniques to find and screen glitches on asynchronous paths, including single-signal and multiple-signal reconvergence, and clock/data reconvergence.NEXT MODULE >