The shrinking of technology nodes has caused an inversion of parasitic concerns where once the cell delay dominated the interconnect delay, now the interconnect delay dominates the cell delay. Likewise, in EDA tools, technology nodes down to submicron had silicon vendors primarily concerned with productivity and runtimes, just to name couple.More >
How often have you come across the scenario where your block or full chip timing is clean or close to clean and then you get constraint drop from constraints owner saying, “not much change in the constraints”? To your surprise after using the new constraints you see thousands of timing violations.
Getting clock relationships correct is very important. In order to get the “set_clock_groups” constraints correct the designer must specify the correct clock pair relationship. If the relationship is incorrect it could lead to over pessimism in Crosstalk/SI analysis, or worse, false path between synchronous clocks.