"Ausdia developed the Timing Verification and signoff environment from ground up for a highly complex, hierarchical chip project. This chip included numerous clocks, high speed interfaces, and 3rd party soft / hard IP cores from various vendors. Ausdia did a great job of putting everything together to verify, and signoff timing for every scenario. Overall, it was a very successful engagement."
Michael Raam - Sr. VP of Engineering
Mobilygen Corp (now part of Maxim)
"Ausdia worked closely with my design team to drive several highly complex blocks through synthesis, constraints and physical implementation. They also contributed heavily to fullchip timing verification and external IP timing verification. They played a big part in the project's success, and I highly recommend their work."
Amal Bommireddy - VP Engineering
"Ausdia was brought in to help finish off some high-priority items, including chip assembly, interface timing verification and toplevel timing closure. I was impressed with their work, and thanks partly to  their efforts we taped out a 1.3B transistor chip that worked first-time  at above the performance target anticipated. Highly recommended."
John B - VP Engineering
Innovative Silicon Valley Server Startup
"We like using constraints cleanup tools like Ausdia Timevision. A lot can and should be done on fullchip STA much earlier in the design cycle, without solely depending on Primetime, Tempus, or other signoff STA tools."
Mehul Mistry -
Broadcom, Inc. - San Jose, CA
"You saved me four months, at minimum."
Sundari Mitra - EVP Engineering
Mosys Inc
"Ausdia worked with us on the implementation phase of a complex controller chip project. I was highly impressed with the quality of work, and timely delivery of all scheduled tasks. Ausdia played a critical role in ensuring the project's huge success, and I highly recommend them."
Stan - Sr. Director ASIC Engineering
Fortune 500 electronics company
"We used Ausdia on a project to implement the digital portion two chips for space research. Due to the use of special layout rules and standard cell libraries, it was highly complex to put together these chips using industry standard Place & Route tools. However, Ausdia used its expertise and experience to make it all work, and helped up tapeout successfully on schedule. I was very satisfied with what Ausdia delivered, in terms of both quality of results and schedule."
Peter Denes - Director of Engineering
Berkeley Labs
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