Ausdia Inc is focused on delivering standout timing constraint development, verification and management solutions that complement all implementation and timing signoff flows. Ausdia's groundbreaking approach represents a new way for STA developers and users to work, enabling massive productivity gains to be realized across the design flow.
Constraint Synthesis and Verification
Timevision represents a new way for STA engineers to massively increase their producivity - by operating as constraint synthesizers, rather than line-by-line writers and debuggers. Timevision also integrates a variety of formal, structural and simulation-based technologies to aid STA engineers in the quick and confident development of constraints from high-level data.
Timevision brings this same capability to RTL designers, who are often under more pressure to be involved with timing closure (but lack the time available to dive into gate-level issues), and to implementation engineers trying to make sense of constraints and how best to implement their designs (but lack the detailed knowledge of the design).
Ausdia was founded in 2006 and is headquartered in Sunnyvale, California. The company has a combined experience of over 57 years in EDA development, and 56 years in chip engineering and methodology.