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Deep Chip - Ausdia Timevision vs Spyglass, Fishtail and Excellicon for SDC

May 29th, 2018


Hi, John,

Synopsys Spyglass Constraints is older, very noisy technology now that grew out of the market-leading RTL lint product of Atrenta. A lot of SoC designers reject it because of noise issues, and from our competitive experience has a lot of issues loading very large blocks and the associated runtime hit. That's in addition to needing to generate SGDC from the SDC and hoping the translation matched the original SDC.

Fishtail checks timing exceptions and clock waveforms, but their long runtimes make a real "checking" loop with synthesis hard to justify.

Real Intent claims to have an SDC checking product, but we heard from some of our customers that they had abandoned it.

Excellion ConMan is a newer generation tool that seems to be more focused on constraint generation. Their ConCert tool seems to have check/lint capabilities but competitive data is hard to come by.

If you're going to synthesize large RTL blocks in either Genus-RTL or DCG you need to do fast and deep checks on what you're feeding into synthesis.

Specifically, your "pre-synthesis checker" needs to have:

1. super-fast runtimes. Checking the inputs must take a LOT
less -- ideally, an order of magnitude less -- than the actual
synthesis time. (Why take 6 hours to lint a block that takes
3 hours to synthesize?);

2. directly reading the SDC input to the synthesis tool, and
debugging/reporting that reference to the actual input;

3. a rich set of checks that can be turned on & off as needed;

4. waivable checks, with as minimal an amount of analysis
noise as possible;

5. has to directly correlate with the timing analysis of both
your synthesis and PnR tools, to ensure anything reported
matches timing analysis.

All my rivals fall down on one or more of these requirements. But I'm very happy to report that my Ausdia Timevision SdcCheck tool has been doing these checks on RTL for many years now.

SdcCheck incorporates more than 200 checks, and like its name implies, does *both* the linting of your SDC and checking it's intent. It supports MMMC constraints, Verilog/SystemVerilog/VHDL, and IEEE P.1735 encrypted RTL.

It also includes precise file/line backtracking so you can directly pinpoint in your source RTL any SDC issues.