Founded in 2006, Ausdia’s leadership has a combined
experience of over 60 years in EDA development, chip
engineering and methodology.
As a CEO and co-founder of Ausdia, Sam has been a driving force in the product planning, product development and market analysis for Timevision, the company’s flagship platform. Prior to Ausdia, he held technical lead roles at Azul Systems, where he managed the implementation & physical methodology for three generations of custom SMP processors, from 500 to 900Mhz and 1.2B transistors. Prior to Azul systems Sam held a variety of technical management positions at Reshape, Cosine Communications and Silicon Graphics.
Sam received a Ph.D. in Electronic Engineering from the University of Adelaide, South Australia focused on high-performance asynchronous circuit & logic design and has personally been involved in more than 20 tape-outs from 1um to 28nm.
As CTO and co-founder of Ausdia, Atul brings more than 17 years of technical leadership in guiding Ausdia's architectural vision and product design to align with the company’s business strategies. Prior Ausdia, Atul was the Timing Analysis, Timing Closure and Chip Integration technical lead at Azul Systems, Reshape, nVIDIA Corp. and Sun Microsystems.
As CTO of Ausdia, Atul provides the pivotal technical leadership role in the RTL synthesis to GDS flow/methodology development to ensure customers timely, successful tape-outs of highly complex chips. He has extensive experience working with the research and development teams of major EDA and IP vendors to derive optimal chip & timing closure solutions.
Atul holds a Bachelors in Electrical Engineering from the University of Kentucky and a Masters in Electrical Engineering from Stanford University.
As Director of Field Engineering at Ausdia, Hollis and his team supports customers globally, striving for seamless tool integration, customer training, and prompt response to technical issues. Prior to Ausdia, Hollis was a senior applications engineer for Azuro's flagship product Powercentric CTS tool, which was acquired by Cadence, and spent several years as an EDA methodology developer for AT&T/Lucent Technologies/Agere Systems.
Hollis received a Bachelors in Electrical Engineering from Tuskegee University focused on high frequency analog design, and an MBA from Salem International University.
Keith Mueller has over 25 years of experience in the EDA and semiconductor markets spanning six successful start-ups. Most recently, in July 2009, he became CEO of Tuscany Design Automation. Within three years he managed Tuscany’s acquisition by Dassault Systems, for which he consulted until late 2013.
Prior to Tuscany, Mueller served as VP of worldwide sales and marketing at Apache Design Solutions from 2002 – 2006, starting from $0 revenue and growing the worldwide sales and applications team to achieve an unprecedented 14 consecutive record sales quarters and company profitability. Apache was later acquired by Ansys, Inc for $315M.
Before Apache, Mueller was VP of worldwide sales at Silicon Perspective Corporation (SPC), acquired by Cadence Design Systems, in 2001. Prior to SPC, Mueller was VP of sales at Anagram, Inc., a circuit simulation start-up acquired by Avant! in 1996. He has also served in various sales management positions at Quickturn Corporation (now a Cadence company) and at start-up Silicon Compilers, Inc., purchased by Mentor Graphics in 1991.