News & Events

 

55th Design Automation Conference

EVENTS  |  Apr 6th, 2018
 

Analyzer merges constraints for multiple timing modes

Tech Design Forum: Analyzer merges constraints for multiple timing modes

NEWS  |  Jun 7th, 2016
 

Ausdia Introduces Hierarchical Budget Analysis and Asynchronous Glitch Detection Add-ons to Timevision

Add-ons generate, verify and refine hierarchical timing budgets; screen and locate “glitchy” logic; and reduce analysis noise

NEWS  |  Jun 4th, 2015
 

BRCM Engineering evaluates Ausdia

http://deepchip.com/items/0550-06.html

NEWS  |  May 22nd, 2015
 

Timing Closure Experts Launch New Company, Announce Proven Timing Constraints Platform

Ausdia helps SoC and IC developers make massive productivity gains across the design flow

NEWS  |  Jun 12th, 2013