CDC
The exploding complexity of SoC designs has resulted in mainstream designs with upwards of 500 clocks. Typically, this complexity is only seen at the full-chip level – unit verification only sees designs with a few clocks – and thus the full design is often very difficult to run through CDC analysis because of capacity and performance constraints of unit-level CDC tools.

Timevision-CDC has proven capacity above 500M instances on Gate netlist with designs of over 1000 clocks, and performs a full array of CDC analysis including :
 
Synchronizer location, reconvergence analysis and formal grey-code verification
Data crossing finding and FIFO binding
IP/block based reconvergence analysis to find unintended reconvergences across functional boundaries
Rich waiver creation (including –through point waivers), waiver backtracking and pruning
SDC-based, eliminating the need for duplicate constraints for CDC and Timing
Multi-clock, Multi-mode analysis – no need for single-clock per register
 
Skew Checks
Despite their asynchronous nature, CDC crossings often need to be timing-checked in backend implementation to ensure the latency assumptions around their design are not violated. Timevision’s CDC-timing feature
 
Generates set_max_delay constraints to constrain both the synchronizer and data crossings related to controlled asynchronous crossings
Verifies that all such crossings are covered by set_max_delays in “checking” mode
Generates skew checks for STA tools that cover bit-skew on reconvergent synchronizers as well as latency checks on FIFOs.
 
Value Proposition
Unit-level CDC tools do not allow the “integration” of the chip to be easily verified for CDC, requiring complex hierarchical abstraction flows and duplication of effort to re-discover CDC clocking and exceptions that already exist in the timing environment.

Timevision CDC is build for the capacity, performance and feature-set to enable full-chip, partition and unit CDC verification using structural and formal techniques, and includes an array of IP binning and grey/black-boxing techniques for the most demanding signoff environments.