Hierarchical Management
Most modern SoCs are designed and implemented hierarchically – as a set of 2 or more blocks, integrated together at the full-chip level, with some SoCs having upwards of 100 blocks and 3 levels of hierarchy. All blocks are required to have timing constraints for synthesis, place/route and STA, along with the full-chip integration level needed for signoff.

Timevision can verify the consistency of multiple levels of hierarchy, for all blocks in the design.
 
 
Additionally, Timevision can propagate timing constraints down in the hierarchy (“demotion”), either from scratch or incrementally if partial block constraints already exist. Alternatively, timing constraints can be propagated up the hierarchy (“promotion”) to the partition or chip-level context, including complex boundary exceptions that are vexing for integration engineers. Timevision includes a broad range of programmability to make the integration process fit the designer’s expectation, allowing almost-manually-tuned levels of control over the integration process.

Once constraints are propagated, the budgets of the blocks need to be created and managed. Timevision uses logic-level information and toplevel timing constraints to drive the creation of IO budgets at the partition- and block-levels.
 
 
Budgets are adjusted due to various reasons at the blocklevel, however, the chip-integrator needs to ensure that the budgets do not result in the over-allocation or under-allocation of total available time when the blocks are integrated in the chip. Timevision-BudgetRefine allows the budgets to be verified for accuracy (i.e. no over- or under-constrained budgets), as well as automated proportional adjustment if problems are flagged at the chip level.
 
Value Proposition
Differences in timing environments between blocks and the “chip” signoff can cause late stage ECOs (and schedule impact) as the differences are manually, painfully uncovered by deduction, or can cause chip failures – where the block/IP designer expected certain paths to be timed, but the chip added timing exceptions that cover those paths. Late-stage ECO & closure headaches can be easily avoided by verifying block-to-chip consistency and using the Budgets feature to verify that no under-constrained paths exist in the chip.