Timevision™ Modules

A solution for constraints development and verification, allowing
system-on-chip (SoC) and integrated circuit (IC) developers to
make massive productivity gains across the design flow.

SOC Budgeter Check SDC Formal SDC SoC Hierarchy Mode-Merge Extracted Timing Model (ETM) Diff SDC Multi-Mode Coverage Design-For-Test (DFT) Clock Domain Crossing (CDC) Glitch

SoC Hierarchy

SoCs have incorporated hierarchical design techniques for some time – using multiple, smaller blocks to close timing, with a “top-level” that incorporates all the blocks and is the ultimate design that is taped out. However, the creation and verification of timing constraints across the disparate hierarchies becomes paramount in such flows, since inconsistent SDCs will cause the resulting blocks to not line up with the tape out requirements of the top-level design.

Timevision SoC Hierarchy performs SDC consistency checking between top-level and an arbitrary number of blocks – including thorny issues such as boundary constraint checking – as well as performing constraint integration (bottom up design) and constraint demotion (top-down design).

NEXT MODULE >

Resource Available

SoC Hierarchy

Verifying clock groups between the top level and block level

VISIT RESOURCE LIBRARY >