News & Events


Deep Chip - Ausdia Timevision vs Spyglass, Fishtail and Excellicon for SDC

7nm closure is going to be a real bear! read more of the different between Timevision and competitors tools

NEWS  |  May 29th, 2018

EDACafe: Video interview at DAC with CEO, Sam Appleton

Learn about Ausdia and new Budgeter module @ DAC 2018.

NEWS  |  Jul 27th, 2018

Ausdia Theater Presentations at DAC

EVENTS  |  May 19th, 2018

Analyzer merges constraints for multiple timing modes

Tech Design Forum: Analyzer merges constraints for multiple timing modes

NEWS  |  Jun 7th, 2016

Ausdia Introduces Hierarchical Budget Analysis and Asynchronous Glitch Detection Add-ons to Timevision

Add-ons generate, verify and refine hierarchical timing budgets; screen and locate “glitchy” logic; and reduce analysis noise

NEWS  |  Jun 4th, 2015

BRCM Engineering evaluates Ausdia

NEWS  |  May 22nd, 2015

Timing Closure Experts Launch New Company, Announce Proven Timing Constraints Platform

Ausdia helps SoC and IC developers make massive productivity gains across the design flow

NEWS  |  Jun 12th, 2013